IDTF1953 Datasheet, PDF (4/17 Pages) Integrated Device Technology – 6-bit Digital Step Attenuator

F1953
DATASHEET
6-bit Digital Step Attenuator
SERIAL CONTROL
400 to 4000 MHz IDTF1953
Serial mode is selected when VMODE is pulled high (> VIH), In serial mode the F1953 attenuation setting is programmed
via the 3 wire bus (LE, CLK, DATA). In serial mode data is clocked in MSB first. Note the timing diagram below.
Note – The IDTF1953 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device
is not being programmed. When Latch enable is high (> VIH), the CLK input is disabled and DATA will not be clocked
into the shift register. It is recommended that LE be pulled high (> VIH) when the device is not being programmed.
SERIAL REGISTER DEFAULT CONDITION
If the device is powered up in Serial Mode, the device will default to whatever attenuation state is defined by the six
parallel data input pins D5,D4,D3,D2,D1,D0 thus allowing any attenuation setting to be specified as the power up state.
SERIAL REGISTER TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue)
V_MODE
CLK
1 23456789
Spec
Interval
AB
LE
CD
Data Word
Latched into
Active Register
DATA
Data Word 6 bits
16 dB 8 dB 4 dB 2 dB 1 dB 0.5 dB
D5
MSB
D4 D3 D2 D1 D0
LSB
Polarity:
1 = Attenuation switched IN
0 = Attenuation switched OUT
Time
SERIAL REGISTER TIMING TABLE
Interval
Symbol
A
B
C
D
Description
From rising edge of Vmode to rising edge of CLK for D5
Clock high pulse width
From rising edge of CLK pulse for D0 to LE rising edge
LE minimum pulse width
Min
Spec
20
10
10
30
Max
Spec
Units
nsec
nsec
nsec
nsec
Glitch-Free^TM Digital Step Attenuator
4
Rev2 April2014