IDT8P34S1212I Datasheet, PDF (4/19 Pages) Integrated Device Technology – Twelve low skew, low additive jitter LVDS output pairs

IDT8P34S1212I Data Sheet
1:12 LVDS Output 1.8V Fanout Buffer
Table 4C. Differential Inputs Characteristics, V_DD = 1.8V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
I_IH
Input High CLK0, CLK1,
Current
nCLK0, nCLK1
V_IN = V_DD = 1.89V
I_IL
V_REF
V_PP
V_CMR
Input Low ^{CLK0, CLK1}
Current
nCLK0, nCLK1
Reference Voltage for Input
Bias^{Note 1.}
Peak-to-Peak Voltage^Note3.
Common Mode Input
Voltage^{Note 2. Note 3.}
V_IN = 0V, V_DD = 1.89V
V_IN = 0V, V_DD = 1.89V
I_REF = +100µA, V_DD = 1.8V
V_DD = 1.89V
-10
-150
0.9
0.2
0.9
1. V_REF specification is applicable to the AC-coupled input interfaces shown in Figures 2B and 2C.
2. Common mode input voltage is defined as crosspoint voltage.
3. V_IL should not be less than -0.3V and V_IH should not be higher than V_DD.
Maximum
150
1.30
1.0
V_DD – (V_PP/2)
Units
µA
µA
µA
V
V
V
Table 4D. LVDS DC Characteristics, V_DD = 1.8V ± 5%, T_A = -40°C to 85°C ^{Note 1.}
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
V_OD
Differential Output Voltage
outputs loaded with 100
247
454
V_OD
V_OD Magnitude Change
50
V_OS
Offset Voltage
1.00
1.40
V_OS
V_OS Magnitude Change
50
1. Output drive current must be sufficient to drive up to 30cm of PCB trace (assume nominal 50 impedance).
Units
mV
mV
V
mV
IDT8P34S1212NLI REVISION A JANUARY 20, 2014
4
©2014 Integrated Device Technology, Inc.