IDT8P34S1212I Datasheet, PDF (1/19 Pages) Integrated Device Technology – Twelve low skew, low additive jitter LVDS output pairs

1:12 LVDS Output 1.8V Fanout Buffer
IDT8P34S1212I
DATA SHEET
General Description
The IDT8P34S1212I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1212I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1212I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and twelve low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
• Twelve low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential CLK0, CLK1 pairs can accept the following differential
input levels: LVDS, CML
• Maximum input clock frequency: 1.2GHz (maximum)
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 10ps (typical)
• Propagation delay: 340ps (typical)
• Low additive phase jitter, RMS; f_REF = 156.25MHz, V_PP = 1V,
12kHz- 20MHz: 41fs (typical)
• Maximum device current consumption (I_DD): 227mA (maximum)
@ 1.89V
• Full 1.8V supply voltage
• Lead-free (RoHS 6), 40-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
V_DD
CLK0
nCLK0
f_REF
V_DD
CLK1
nCLK1
SEL
V_REF
V_REF
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
Pin Assignment
30 29 28 27 26 25 24 23 22 21
V_DD 31
Q8 32
nQ8 33
Q9 34
nQ9 35
Q10 36
nQ10 37
Q11 38
nQ11 39
V_DD 40
IDT8P34S1212I
40-Lead VFQFN
6.0mm x 6.0mm x 0.90mm
package body
4.65mm x 4.65mm ePad Size
NL Package
Top View
1 2 3 4 5 6 7 8 9 10
20 V_DD
19 nQ3
18 Q3
17 nQ2
16 Q2
15 nQ1
14 Q1
13 nQ0
12 Q0
11 V_DD
IDT8P34S1212NLI REVISION A JANUARY 20, 2014
1
©2014 Integrated Device Technology, Inc.