ICS9DBL411 Datasheet, PDF (4/9 Pages) Integrated Device Technology – Four Output Differential Fanout Buffer for PCI Express Gen 1 & 2

ICS9DBL411
Four Output Differential Buffer for PCI Express
Advance Information
MLF Pin Description
PIN #
(MLF)
1
2
PIN NAME
VDDA
GNDA
3 OE3#
4 DIF3C_LPR
5 DIF3T_LPR
6 VDD_IO
7 GND
8 DIF2C_LPR
9 DIF2T_LPR
10 OE2#
11 DIF1C_LPR
12 DIF1T_LPR
13 OE1#
14 GND
15 VDD_IO
16 DIF0C_LPR
17 DIF0T_LPR
18 OE0#
19 DIF_INC
20 DIF_INT
PIN TYPE
DESCRIPTION
PWR
GND
IN
OUT
OUT
PWR
GND
OUT
OUT
IN
OUT
OUT
IN
GND
PWR
OUT
OUT
IN
IN
IN
3.3V Power for the Analog Core
Ground for the Analog Core
Output Enable for DIF3 output. Control is as follows:
0 = enabled, 1 = Low-Low
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
Power supply for low power differential outputs, nominal 1.05V to 3.3V
Ground pin
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
Output Enable for DIF2 output. Control is as follows:
0 = enabled, 1 = Low-Low
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
Output Enable for DIF1 output. Control is as follows:
0 = enabled, 1 = Low-Low
Ground pin
Power supply for low power differential outputs, nominal 1.05V to 3.3V
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to
GND needed)
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND
needed)
Output Enable for DIF0 output. Control is as follows:
0 = enabled, 1 = Low-Low
Complement side of differential input clock
True side of differential input clock
IDT^TM/ICS^TM Four Output Differential Buffer for PCI Express
4
1250A—07/31/07