ICS91305I Datasheet, PDF (4/9 Pages) Integrated Circuit Solution Inc – High Performance Communication Buffer

ICS91305I
HIGH PERFORMANCE COMMUNICATION BUFFER
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
Output period
Input period
t1
With CL=30pF
t1
With CL=30pF
100.00
(10)
100.00
(10)
Duty Cycle¹
Dt1
Measured at 1.4V; CL=30pF
40.0
50
Duty Cycle¹
Dt2
Measured at VDD/2 Fout
<66.6MHz
45
50
Rise Time¹
tr1
Measured between 0.8V and 2.0V:
CL=30pF
1.2
Fall Time¹
tf1
Measured between 2.0V and 0.8V;
CL=30pF
1.2
Delay, REF Rising
Edge to CLKOUT
Dr1
Measured at 1.4V
0
Rising Edge^{1, 2}
Output to Output
Skew¹
Tskew
All outputs equally loaded,
CL=20pF
Device to Device
Skew¹
Tdsk-Tdsk
Measured at VDD/2 on the
CLKOUT pins of devices
0
Cycle to Cycle
Jitter¹
Tcyc-Tcyc
Measured at 66.66 MHz, loaded
outputs
PLL Lock Time¹
t
LOCK
Stable power supply, valid clock
presented on REF pin
Jitter; Absolute
Jitter¹
Jitter; 1 - Sigma¹
Tjabs
Tj1s
@ 10,000 cycles
C_L = 30pF
@ 10,000 cycles
C_L = 30pF
-200
70
14
MAX
7.5
(133)
7.5
(133)
60
55
1.5
1.5
±350
250
700
200
1.0
200
60
UNITS
ns
(MHz)
ns
(MHz)
%
%
ns
ns
ps
ps
ps
ps
ms
ps
ps
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. REF input has a threshold voltage of 1.4V
3. All parameters expected with loaded outputs
IDT® HIGH PERFORMANCE COMMUNICATION BUFFER
4
ICS91305I
REV G 090612