ICS86004-02 Datasheet, PDF (4/10 Pages) Integrated Device Technology – 62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER

ICS86004-02
62.5MHz TO 250MHz, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PRELIMINARY
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
t_PD
t(Ø)
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
F_SEL = 0
F_SEL = 1
PLL_SEL = 0V,
Bypass Mode
PLL_SEL = 3.3V
PLL_SEL = 0V
125
62.5
5.8
330
60
250
MHz
125
MHz
ns
ps
ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4
F_SEL = 0
F_SEL = 1
40
ps
35
ps
t_L
PLL Lock Time
1
mS
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL = 0
F_SEL = 1
550
ps
50
%
50
%
NOTE 1: Measured from the differential input crossing point to the output at V_DDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
3.3V±5%,
V
DDO
= 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
F_SEL = 0
125
250
F_SEL = 1
62.5
125
t_PD
Propagation Delay; NOTE 1
PLL_SEL = 0V,
Bypass Mode
6.2
t(Ø)
Static Phase Offset; NOTE 2, 4
PLL_SEL = 3.3V
285
tsk(o) Output Skew; NOTE 3, 4
PLL_SEL = 0V
45
F_SEL = 0
45
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4
F_SEL = 1
35
t_L
PLL Lock Time
1
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
500
F_SEL = 0
50
F_SEL = 1
50
NOTE 1: Measured from the differential input crossing point to the output at V_DDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
MHz
ns
ps
ps
ps
ps
mS
ps
%
%
IDT^™ / ICS^™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
4
ICS86004AG-02 REV A NOVEMBER 3, 2006