ICS8402I Datasheet, PDF (4/19 Pages) Integrated Circuit Systems – 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER

ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 2. Pin Characteristics
Symbol
C_IN
C_PD
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
R_PULLUP Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
R_OUT
Output Impedance
Test Conditions
V_DD, V_DDO = 3.465V
V_DD = 3.465V, V_DDO = 2.625V
V_DDO = 3.465V
V_DDO = 2.625V
Minimum
5
Typical
4
13
11
51
51
7
7
Maximum
12
Units
pF
pF
pF
kΩ
kΩ
Ω
Ω
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR nP_LOAD M
N S_LOAD S_CLOCK
H
X
X
X
X
X
L
L
Data Data
X
X
L
↑
Data Data
L
X
L
H
X
X
L
↑
L
H
X
X
↑
L
L
H
X
X
↓
L
L
H
X
X
L
X
L
H
X
X
H
↑
NOTE:
L = LOW
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
4
ICS8402AYI REV. A OCTOBER 16, 2007