ICS8402I Datasheet, PDF (3/19 Pages) Integrated Circuit Systems – 350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER

ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
1
M5
2, 3, 4, 28, M6, M7, M8, M0,
29, 30, 31, 32 M1, M2, M3, M4
5, 6
N0, N1
7
nc
8, 16
GND
9
TEST
10
V_DD
11, 12
OE1, OE0
13
14, 15
V_DDO
Q1, Q0
17
MR
18
S_CLOCK
19
S_DATA
20
S_LOAD
21
V_DDA
22
XTAL_SEL
23
TEST_CLK
24,
XTAL_OUT
25
XTAL_IN
26
nP_LOAD
27
VCO_SEL
Type
Description
Input
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
Pulldown ^{LVCMOS/LVTTL interface levels.}
Input Pulldown _{Determines output divider value as defined in Table 3C, Function Table.}
Unused
LVCMOS/LVTTL interface levels.
Power
No connect.
Output
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Power
Core supply pin.
Input
Pullup
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in Tri-State. See Table 3D,
OE Function Table. LVCMOS / LVTTL interface levels.
Power
Output supply pin.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Input
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When Logic LOW, the internal dividers and the
outputs are enabled. Assertion of MR does not affect loaded M, N, and T
values. LVCMOS/LVTTL interface levels.
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Input
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Power
Analog supply pin.
Input
Pullup
Selects between crystal oscillator or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS/LVTTL interface levels.
Input Pulldown Test clock input. LVCMOS/LVTTL interface levels.
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Input
Input
Parallel load input. Determines when data present at M8:M0 is loaded into M
Pulldown divider, and when data present at N1:N0 sets the N output divider value.
LVCMOS/LVTTL interface levels.
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
3
ICS8402AYI REV. A OCTOBER 16, 2007