ICS83948I Datasheet, PDF (4/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

ICS83948I
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4B. DC Characteristics, V_DD = V_DDO = 3.3V ± 0.3V, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
V_IH
V_IL
V_PP
V_CMR
I_IN
V_OH
V_OL
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Input Current
Output High Voltage
Output Low Voltage
I_OH = -20mA
I_OL = 20mA
2
-0.3
0.15
GND + 0.5
2.5
NOTE 1: V_IL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V_IH.
Typical
Maximum
V_DD + 0.3
0.8
1.3
V_DD – 0.85
±100
0.4
Units
V
V
V
V
µA
V
V
AC Electrical Characteristics
Table 5. AC Characteristics, V_DD = V_DDO = 3.3V ± 0.3V, T_A = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum
f_MAX
Output Frequency
CLK/nCLK;
NOTE 1A
ƒ  150MHz
2.25
t_PD
Propagation Delay
LVCMOS_CLK;
NOTE 1B
ƒ  150MHz
2
tsk(o)
tsk(pp)
Output Skew; NOTE 2, 6
Part-to-Part Skew; ^CLK/nCLK
NOTE 3, 6
LVCMOS_CLK
Measured on
Rising Edge @ V_DDO/2
Measured on
Rising Edge @ V_DDO/2
t_R / t_F
t_PW
t_PZL, t_PZH
t_PLZ, t_PHZ
t_S
Output Rise/Fall Time
Output Pulse Width
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Clock Enable
Setup Time;
NOTE 5
CLK_EN to
CLK/nCLK
CLK_EN to
LVCMOS_CLK
0.8V to 2V
ƒ < 150MHz
0.2
t_Cycle/2 - 800
1
0
Clock Enable
CLK/nCLK to
CLK_EN
1
t_H
Hold Time;
NOTE 5
LVCMOS_CLK to
CLK_EN
1
Typical
Maximum
250
3.75
4
350
1.5
2
1.0
t_Cycle/2 + 800
11
11
Units
MHz
ns
ns
ps
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
NOTE 1A: Measured from the differential input crossing point to V_DDO/2 of the output.
NOTE 1B: Measured from V_DD/2 or crosspoint of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
4
ICS83948AYI REV. C NOVEMBER 14, 2012