ICS83948I Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

ICS83948I
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
1
CLK_SEL
2
3
4
5
6
7
8, 12, 16,
20, 24, 28, 32
9, 11, 13,
15, 17, 19,
21, 23, 25,
27, 29, 31
10, 14, 18,
22, 26, 30
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V_DD
GND
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
V_DDO
Type
Input
Pullup
Input
Input
Input
Input
Input
Power
Pullup
Pullup
Pulldown
Pullup
Pullup
Description
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Clock enable pin. LVCMOS/LVTTL interface levels.
Output enable pin. LVCMOS/LVTTL interface levels.
Positive supply pin.
Power
Power supply ground.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
C_PD
Power Dissipation Capacitance
(per output)
R_OUT
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
25
7
Maximum
Units
pF
k
k
pF

Function Tables
Table 3A. Clock Select Function Table
Control Input
Clock
CLK_SEL
CLK/nCLK
LVCMOS_CLK
0
Selected
De-selected
1
De-selected
Selected
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
2
ICS83948AYI REV. C NOVEMBER 14, 2012