IDT72V3654 Datasheet, PDF(33/37 Page) Integrated Device Technology – 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2

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IDT72V3654 Datasheet, PDF (33/37 Pages) Integrated Device Technology – 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2

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IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

CLKB

CSB

W/RB

MBB

ENB

B0-B35

tENS1

tENS2

tDS

tENH

tDH

COMMERCIAL TEMPERATURE RANGE

CLKA

MBF2

tPMF

CSA

W/RA

tPMF

MBA

tENS2

tENH

ENA

A0-A35

tEN

tPMR

tMDV

FIFO2 Output Register

tDIS

W1 (Remains valid in Mail 2 Register after read)

4664 drw30

NOTE:

1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are donât care inputs). In this first case A0-A17 will have valid data

(A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are donât care inputs). In this second

case, A0-A8 will have valid data (A9-A35 will be indeterminate).

Figure 28. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)

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