IDT72V3654 Datasheet, PDF(18/37 Page) Integrated Device Technology – 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2

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IDT72V3654 Datasheet, PDF (18/37 Pages) Integrated Device Technology – 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2

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IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKA

CLKB

MRS1

BE/FWFT

FS2,

FS1,FS0

FFA/IRA

EFB/ORB

AEB

AFA

MBF1

tRSTS

tRSF

tWFF

tRSTH

tBES

tBEH

tFSS

tFSH

0,1

tFWS

tREF (3)

FWFT

tWFF

RTM LOW

4664 drw 05

NOTES:

1. FIFO2 Master Reset (MRS2) is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset, MRS1 must toggle simultaneously with MRS2.

2. PRS1 must be HIGH during Master Reset.

3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.

Figure 3. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes)

CLKA

CLKB

PRS1

FFA/IRA

tRSTS

EFB/ORB

AEB

tRSF

AFA

tRSF

MBF1

RTM LOW

tWFF

tRSTH

tREF(3)

NOTES:

1. Partial Reset is performed in the same manner for FIFO2.

2. MRS1 must be HIGH during Partial Reset.

3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.

Figure 4. FIFO1 Partial Reset(1) (IDT Standard and FWFT Modes)

tWFF

4664 drw 06

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