8T49N241_16 Datasheet, PDF (32/68 Pages) Integrated Device Technology – FemtoClock NG Universal Frequency Translator

8T49N241 Datasheet
Table 7L. Power Down Control Register Bit Field Locations and Descriptions
Power Down Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
006C
Rsvd
006D
Rsvd
006E
Rsvd
006F
Rsvd
Q3_DIS
Q2_DIS
0070
Rsvd
DPLL_DIS
D1
LCKMODE
CLK1_DIS
Q1_DIS
DSM_DIS
D0
DBL_DIS
CLK0_DIS
Q0_DIS
CALRST
Bit Field Name
LCKMODE
DBL_DIS
CLKm_DIS
Qm_DIS
DPLL_DIS
DSM_DIS
CALRST
Rsvd
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power Down Control Register Block Field Descriptions
Default Value Description
Controls the behavior of the LOL alarm deassertion:
0b
0 = LOL alarm deasserts once PLL is locked
1 = LOL alarm deasserts once PLL is locked and output clocks are stable
Controls whether crystal input frequency is doubled before being used in PLL:
0b
0 = 2x Actual Crystal Frequency Used
1 = Actual Crystal Frequency Used
Disable Control for Input Reference m (m = 0, 1):
0b
0 = Input Reference m is Enabled
1 = Input Reference m is Disabled
Disable Control for Output Qm, nQm (m = 0, 1, 2, 3):
0 = Output Qm, nQm functions normally
0b
1 = All logic associated with Output Qm, nQm is Disabled & Driver in High-Impedance
state
Disable Control for Digital PLL:
0b
0 = Digital PLL Enabled
1 = Digital PLL Disabled
Disable Control for Delta-Sigma Modulator for Analog PLL:
0b
0 = DSM Enabled
1 = DSM Disabled
Reset Calibration Logic for Analog PLL:
0b
0 = Calibration Logic for Analog PLL Enabled
1 = Calibration Logic for Analog PLL Disabled
-
Reserved. Always write 0 to this bit location. Read values are not defined.
©2016 Integrated Device Technology, Inc.
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Revision 6, October 31, 2016