IDT82V2108 Datasheet, PDF (30/272 Pages) Integrated Device Technology – T1 / E1 / J1 OCTAL FRAMER

IDT82V2108 T1 / E1 / J1 OCTAL FRAMER
INDUSTRIAL
TEMPERATURE RANGES
packet was received. This bit (PKIN) is set regardless of the status of
the FCS condition or if there are an integer or non-integer number of
bytes stored in the FIFO.
The HDLC packet can be forced to terminate for four reasons:
1. The 7F abort sequence is received;
2. More than 15 successive logic ones are received in the data
stream;
3. Set the TR (b1, E1-048H) to logic 1;
4. Set the EN (b0, E1-048H) from logic 1 to logic 0 and back to logic
1.
All the above methods can deactivate the HDLC link immediately and
the latter two means can also clean the FIFO and interrupts. A new
search for the 7E opening flag is also initiated.
The interrupt sources in this block are:
1. Receiving the first 7E opening flag sequence which terminates all
ones data and activates the HDLC link;
2. Receiving the 7E closing flag sequence;
3. Receiving the abort sequence;
4. Exceeding the set point of the FIFO which is defined in the
INTC[6:0] (b6~0, E1-049);
5. Over-writting the FIFO.
Any one of the interrupt sources will assert the INTR (b0, E1-04AH)
high. Then the INT pin will be low to report the interrupt if the INTE (b7,
E1-049H) is logic 1.
3.5.2 T1 / J1 MODE
In the SF format, there is no HDLC link.
In the ESF format, two HDLC Receiver blocks (#1 and #2) are em-
ployed for each framer to extract the HDLC link. Before selecting the
HDLC link, the TXCISEL (b3, T1/J1-00DH) should be set to 0. Thus, the
configuration of the Link Control and Bits Select registers (addressed
from 070H to 071H) is for the RHDLC. Then, selected by the
RHDLCSEL[1:0] (b7~6, T1/J1-00DH), one of the two HDLC Receiver
blocks are accessable to the microprocessor. The HDLC#1 extracts the
HDLC link in the DL of the F-bit (its position is shown in Table - 4). The
HDLC#2 extracts the HDLC link from one of the channels which position
is selected as follows:
1. Set the DL2_EVEN (b7, T1/J1-070H) and/or the DL2_ODD (b6,
T1/J1-070H) to select the even and/or odd frames;
2. Set the DL2_TS[4:0] (b4~0, T1/J1-070H) to select the channel of
the assigned frame;
3. Set the DL2_BIT[7:0] (b7~0, T1/J1-071H) to select the bits of the
assigned channel.
All the functions of the selected HDLC Receiver block can be ena-
bled only if the EN (b0, T1/J1-054H) is set to logic 1.
The structure of the HDLC packet is the same as it is described in
the E1 mode (refer to Figure - 3).
A FIFO buffer is used to store the HDLC packet, that is, to store the
data whose stuffed zeros have been removed and the FCS. However,
when the address matching is enabled, the first and/or second byte
compares with the address setting in the PA[7:0] (b7~0, T1/J1-058H)
and the SA[7:0] (b7~0, T1/J1-059H) and only the data matching the se-
lection in the MEN (b3, T1/J1-054H) and the MM (b2, T1/J1-054H) are
stored into the FIFO. When the address matching is disabled, the entire
HDLC packet is stored. The first 7E opening flag which activates the
HDLC link and the 7F abort sequence which deactivates the HDLC link
will also be converted into dummy bytes and stored in the FIFO. These
two types of flags will also assert the COLS (b5, T1/J1-056H) to indicate
the HDLC link status change. The content in the FIFO is read in the
RD[7:0] (b7~0, T1/J1-057H), and the status of the bytes will be reflected
in the PBS[2:0] (b3~1, T1/J1-056H). Both of the two registers can’t be
accessed at a rate greater than 1/15 of the XCK rate.
The depth of the FIFO is 128 bytes. When the FIFO is empty, the FE
(b7, T1/J1-056H) will be set. If data are still written into the FIFO when
the FIFO is already full, the FIFO will be over-written. The over-written
condition will be indicated by the OVR (b6, T1/J1-056H) and force the
FIFO to be cleared.
A logic 1 in the PKIN (b4, T1/J1-056H) indicates a non-abort HDLC
packet was received whether there were FCS errors or non-integer
number if bytes errors in it or not.
The HDLC packet can be forced to terminate by four means:
1. The 7F abort sequence is received;
2. More than 15 successive logic ones are received in the data
stream;
3. Set the TR (b2, T1/J1-054H) to logic 1;
4. Set the EN (b1, T1/J1-054H) from logic 1 to logic 0 and back to
logic 1.
All the above methods can deactivate the HDLC link immediately and
the latter two methods can also clear the FIFO and interrupts. A new
search for the 7E opening flag is also initiated.
The interrupt sources in this block are:
1. Receiving the first 7E opening flag sequence which terminates the
all ones data and activates the HDLC link;
2. Receiving the 7E closing flag sequence;
3. Receiving the abort sequence;
4. Exceeding the set point of the FIFO which is defined in the
INTC[6:0] (b6~0, T1/J1-055H);
5. Over-writting the FIFO.
Any one of the interrupt sources will assert the INTR (b0, T1/J1-
056H) high. Then the INT pin will be driven low to report the interrupt if
the INTE (b7, T1/J1-055H) is logic 1.
3.6 BIT-ORIENTED MESSAGE RECEIVER (RBOM) - T1
/ J1 ONLY
The Bit Oriented Message (BOM) can only be received in the ESF
format in T1/J1 mode. The standard of the BOM is defined in ANSI
T1.403 and in TR-TSY-000194. This block of each framer operates inde-
pendently.
The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of
the F-bit in the ESF format (refer to Table-4). The six ‘X’s represent the
message. The BOM is declared only when the pattern is matched and
the received message is identical 4 out of 5 times or 8 out of 10 times.
The identification time is selected by the AVC (b1, T1/J1-02AH). After the
BOM is declared, the BOM is loaded into the BOC[5:0] (b5~0, T1/J1-
02BH). However, the BOM does not include all ones code in both T1 and
J1 mode.
When the BOM is converted into non-BOM, the received data will be
idle code. The pattern of the idle code is ‘FFFF’ in T1 mode and ‘FF7E’
in J1 mode. When the received data is 4 out of 5 times or 8 out of 10
times identical with the pattern, the idle code is declared. The identifica-
tion time is selected by the AVC (b1, T1/J1-02AH).
There are two interrupt sources in this block. When the BOM is de-
clared, the BOCI (b6, T1/J1-02BH) will indicate it. When the idle code is
declared, the IDLEI (b7, T1/J1-02BH) will indicate it. If the BOCE (b0,
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