ICS853S004I Datasheet, PDF (3/20 Pages) Integrated Device Technology – Low Skew, 1-to-4, Differential-to-2.5V, 3.3V LVPECL Fanout Buffer

ICS853S004I Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
nEN
Q[0:3]
nQ[0:3]
1
Disabled; Low
Disabled; High
0
Enabled
Enabled
After nEN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the PCLK/nPCLK input as described in Table 3B.
nEN
nPCLK
V_PP
PCLK
V_DD/2
t_S
t_PD
nQ[0:3]
Q[0:3]
Figure 1. nEN Timing Diagram
V_DD/2
t_H
Table 3B. Clock Input Function Table
Inputs
PCLK
nPCLK
0
1
1
0
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
0
Biased; NOTE 1
1
Outputs
Q0:Q3
nQ0:nQ3
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-ended Levels.
ICS853S004AKI May 27, 2017
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