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| ICS8512061I Datasheet, PDF (3/17 Pages) Integrated Device Technology – SINGLE CHANNEL 0.7V DIFFERENTIALTO-LVTTL TRANSCEIVER | |||
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ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VIH
Input High Voltage
VIL
Input Low Voltage
IN
IIH
Input High Current
DIR_SEL
IN
IIL
Input Low Current
DIR_SEL
VOH
Output High Voltage;
NOTE 1
QB
VDD = VIN = 3.6V
VDD = VIN = 3.6V
VDD = 3.6V, VIN = 0V
VDD = 3.6V, VIN = 0V
VDD = 3.6V
2
-0.3
-150
-5
2.6
VOL
Output Low Voltage;
NOTE 1
QB
VDD = 3.6V
Typical
Maximum
VDD + 0.3
0.8
5
150
0.5
Units
V
V
µA
µA
µA
µA
V
V
NOTE: Outputs terminated with 50⦠to VDD/2. See Parameter Measurement Information Section, Output Load Test Circuit diagram.
Table 3C. Differential DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VPP
VCMR
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
DIR_SEL = 0
DIR_SEL = 0
0.15
GND + 0.5
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Typical
Maximum
1.3
VDD â 0.85
Units
V
V
AC Electrical Characteristics
Table 4A. LVTTL (QB) Output Mode, Receiver AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
FMAX
Output Frequency
250
tPD
Propagation Delay, NOTE 1
QA/nQA to QB
1.7
2.5
tjit
Buffer Additive Phase Jitter, RMS
100MHz, Integration Range: 12kHz
â 20MHz
0.23
tR/tF
Output Rise/Fall Time
odc
Output Duty Cycle
20% - 80%
200
700
40
60
NOTE 1: Measured from VDD/2 input cross point to the output at VDD/2.
Units
MHz
ns
ps
ps
%
IDT⢠/ ICS⢠TRANSCEIVER
3
ICS8512061AGI REV. B NOVEMBER 19, 2008
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