ICS84329-01 Datasheet, PDF (3/20 Pages) Integrated Device Technology – 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Name
Type
Description
M0, M1, M2, M3,
M4, M5, M6, M7, M8
N0, N1
Input
Input
Pullup
Pullup
M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
V_EE
TEST
Power
Output
Negative supply pins.
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
V_CC
nFOUT, FOUT
S_CLOCK
S_DATA
S_LOAD
Power
Output
Input
Input
Input
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Pulldown
Clocks the serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Pulldown
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
V_CCA
nc
Power
Unused
Analog supply pin.
No connect.
XTAL1, XTAL2
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
nP_LOAD
Input
Pullup
Parallel load input. Determines when data present at M8:M0 is loaded into
the M divider, and when data present at N1:N0 sets the N output divider value.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
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REV. D AUGUST 7, 2010