9FGL04_16 Datasheet, PDF (3/18 Pages) Integrated Device Technology – 4-output 3.3V PCIe Clock Generator

Pin Descriptions
Pin#
1
2
3
4
5
Pin Name
GNDXTAL
XIN/CLKIN_25
X2
VDDXTAL3.3
VDDREF3.3
6 vSADR/REF3.3
7 GNDREF
8 GNDDIG
9 VDDDIG3.3
10 SCLK_3.3
11 SDATA_3.3
12 vOE0#
13 DIF0
14 DIF0#
15 GND
16 VDDO3.3
17 vOE1#
18 DIF1
19 DIF1#
20 GNDA
21 VDDA3.3
22 DIF2
23 DIF2#
24 vOE2#
25 VDDO3.3
26 GND
27 DIF3
28 DIF3#
29 vOE3#
30 GND
31 ^CKPWRGD_PD#
32 vSS_EN_tri
33 ePAD
9FGL04 DATASHEET
Type Pin Description
GND GND for XTAL
IN
Crystal input or Reference Clock input. Nominally 25MHz.
OUT
Crystal output.
PWR
PWR
Power supply for XTAL, nominal 3.3V
VDD for REF output. nominal 3.3V.
LATCHED
I/O
Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin
GND
GND
Ground pin for the REF outputs.
Ground pin for digital circuitry
PWR
IN
3.3V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT
OUT
Differential true clock output
Differential Complementary clock output
GND
PWR
Ground pin.
Power supply for outputs,nominal 3.3V.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT
OUT
Differential true clock output
Differential Complementary clock output
GND
PWR
Ground pin for the PLL core.
3.3V power for the PLL core.
OUT
OUT
IN
PWR
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for outputs,nominal 3.3V.
GND
OUT
Ground pin.
Differential true clock output
OUT
IN
GND
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
LATCHED IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND Connect to ground
OCTOBER 19, 2016
3
4-OUTPUT 3.3V PCIE CLOCK GENERATOR