9FGL04_16 Datasheet, PDF (13/18 Pages) Integrated Device Technology – 4-output 3.3V PCIe Clock Generator

9FGL04 DATASHEET
SMBus Table: Stop State Control
Byte 11
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
STP[1]
Bit 0
STP[0]
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
True/Complement DIF Output
Disable State
Type
RW
RW
0
00 = Low/Low
01 = HiZ/HiZ
1
10 = High/Low
11 = Low/High
Default
X
X
X
X
X
X
0
0
SMBus Table: Impedance Control
Byte 12
Name
Bit 7
DIF1_imp[1]
Bit 6
DIF1_imp[0]
Bit 5
Bit 4
Bit 3
DIF0_imp[1]
Bit 2
DIF0_imp[0]
Bit 1
Bit 0
Control Function
DIF1 Zout
DIF1 Zout
Reserved
Reserved
DIF0 Zout
DIF0 Zout
Reserved
Reserved
Type
RW
RW
RW
RW
0
00=33_ DIF Zout
01=85_ DIF Zout
00=33_ DIF Zout
01=85_ DIF Zout
1
10=100_ DIF Zout
11 = Reserved
10=100_ DIF Zout
11 = Reserved
Default
See Note
X
X
See Note
X
X
SMBus Table: Impedance Control
Byte 13
Name
Bit 7
Bit 6
Bit 5
DIF3_imp[1]
Bit 4
DIF3_imp[0]
Bit 3
DIF2_imp[1]
Bit 2
DIF2_imp[0]
Bit 1
Bit 0
Control Function
Reserved
Reserved
DIF3 Zout
DIF3 Zout
DIF2 Zout
DIF2 Zout
Reserved
Reserved
Type
RW
RW
RW
RW
0
00=33_ DIF Zout
01=85_ DIF Zout
00=33_ DIF Zout
01=85_ DIF Zout
1
10=100_ DIF Zout
11 = Reserved
10=100_ DIF Zout
11 = Reserved
Default
X
X
See Note
See Note
X
X
SMBus Table: Pull-up Pull-down Control
Byte 14
Name
Control Function
Bit 7
OE1_pu/pd[1]
OE1 Pull-up(PuP)/
Bit 6
OE1_pu/pd[0]
Pull-down(Pdwn) control
Bit 5
Reserved
Bit 4
Reserved
Bit 3
OE0pu/pd[1]
OE0Pull-up(PuP)/
Bit 2
OE0_pu/pd[0]
Pull-down(Pdwn) control
Bit 1
Reserved
Bit 0
Reserved
Type
RW
RW
RW
RW
0
00=None
01=Pdwn
00=None
01=Pdwn
1
10=Pup
11 = Pup+Pdwn
10=Pup
11 = Pup+Pdwn
Default
0
1
X
X
0
1
X
X
OCTOBER 19, 2016
13
4-OUTPUT 3.3V PCIE CLOCK GENERATOR