8V41N010 Datasheet, PDF (3/26 Pages) Integrated Device Technology – Selectable external crystal or differential

8V41N010 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Name
nc
V_DDO
nc
nc
GND
nc
FSEL_E1
REF_SEL
V_DD
XTAL_IN
XTAL_OUT
PLL_SEL
nc
FSEL_A1
Type
Unused
Power
Unused
Unused
Power
Unused
Input
Pulldown
Input
Power
Crystal
Input
Crystal
Output
Input
Unused
Input
Pullup
Pullup
Pulldown
Description
No internal connection.
Output supply.
No internal connection.
No internal connection.
Power supply ground.
No internal connection.
Selects the QEx, nQEx output frequency. LVCMOS/LVTTL interface levels.
0 = 100MHz (default)
1 = 156.25MHz
Input source control pin. LVCMOS/LVTTL interface levels.
0 = CLK, nCLK
1 = XTAL (default)
Core supply.
Parallel resonant crystal input.
Parallel resonant crystal output.
PLL bypass control pin. LVCMOS/LVTTL interface levels.
0 = Bypass mode
1 = PLL mode (default)
No internal connection.
Selects the QAx, nQAx output frequency. LVCMOS/LVTTL interface levels.
0 = 100MHz (default)
1 = 156.25MHz
15
CLK
Input
Pulldown Non-inverting differential clock input.
16
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to V_DD/2.
17
nc
Unused
No internal connection.
Selects the QBx, nQBx output frequency. LVCMOS/LVTTL interface levels.
18
FSEL_B1
Input
Pulldown 0 = 100MHz (default)
1 = 156.25MHz
19
V_{DDO_QF}
Power
20
QF
Output
QF output supply (LVCMOS/LVTTL).
Single-ended output. 3.3V LVCMOS/LVTTL interface levels.
21
GND
Power
Power supply ground.
22
V_DD
Power
23
GND
Power
Core supply.
Power supply ground.
24
V_{DDO_QA}
Power
25
QA0
Output
Bank A (HCSL) output supply.
Bank A differential output pair. HCSL interface levels.
26
nQA0
Output
Bank A differential output pair. HCSL interface levels.
27
QA1
Output
Bank A differential output pair. HCSL interface levels.
28
nQA1
Output
Bank A differential output pair. HCSL interface levels.
29
GND
Power
Power supply ground.
Active HIGH output enable for Bank A outputs. LVCMOS/LVTTL interface levels.
30
OE_A
Input
Pullup 0 = Bank A outputs disabled/high impedance
1 = Bank A outputs enabled (default)
REVISION 1 06/30/15
3
CLOCK GENERATOR FOR CAVIUM PROCESSORS