8V41N010 Datasheet, PDF (1/26 Pages) Integrated Device Technology – Selectable external crystal or differential

Clock Generator for Cavium Processors
8V41N010
General Description
The 8V41N010 is a PLL-based clock generator specifically designed
for Cavium Networks Octeon II processors. This high performance
device is optimized to generate the processor core reference clock,
the PCI-Express, sRIO, XAUI, SerDes reference clocks and the
clocks for both the Gigabit Ethernet MAC and PHY. The output fre-
quencies are generated from a 25MHz external input source or an
external 25MHz parallel resonant crystal. The industrial temperature
range of the 8V41N010 supports telecommunication, networking,
and storage requirements.
Pin Assignment
DATA SHEET
Features
• Eight selectable 100MHz and 156.25MHz clocks for PCI Express,
sRIO and GbE, HCSL interface levels
• One single-ended QF LVCMOS/LVTTL clock output at 50MHz
• Selectable external crystal or differential (single-ended)
input source
• Crystal oscillator interface designed for 25MHz, parallel
resonant crystal
• Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
• Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
QE0
nQE0
QE1
nQE1
GND
OE_E
nc
FSEL_C1
GND
V_DDA
nc
FSEL_D1
V_DD
nMR
V_DDO
nc
GND
nc
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
55
36
56
35
57
34
58
33
59
32
60
8XXXXXX
31
61
30
62
29
63
8V41N010
28
64
27
65
26
66
25
67
24
68
23
69
22
70
21
71
20
72
19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND
nc
nc
nQB0
QB0
V_{DDO_QB}
OE_A
GND
nQA1
QA1
nQA0
QA0
V_{DDO_QA}
GND
V_DD
GND
QF
V_{DDO_QF}
72-pin, 10mm x 10mm VFQFN Package
8V41N010 REVISION 1 06/30/15
1
NOTE: Exposed pad must always be connected to GND.
NOTE: Pin 1 is located at bottom left corner as shown.
©2015 Integrated Device Technology, Inc.