92HD93 Datasheet, PDF (280/302 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD93
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
7.29.1.4. AIC3 Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions
Register Address
Bit
Label
7:6 RSVD
5
SAEN
4
AUXSWAP
verb F78/778
3
MCLKMS
2:0 MCLK[2:0]
Type Default
Description
RO 00
Reserved
RW 0
1 = Input enabled for I2S Secondary Audio
0 = Input disabled for Secondary Audio
RW 0
Swap Left and Right Samples of Aux Audio Output.
0 = Left sample first in frame
1 = Right sample first in frame
RW 1
MCLK master
0 = MCLK is an input
1 = MCLK is an output (not recommended in Aux Audio Mode
since 24/12MHz rates cant be supported and 112MHz internal
clock is imprecise but is useful for testing.)
RW 001
MCLK rate
000 = 24MHz (HDA BitClk)
001 = 12MHz (HDA BitClk/2)
010 = 22.5792MHz
011 = 11.2896MHZ
100 = 5.6448MHZ
101 = 28.224MHz
110 = 14.112MHz
111 = 7.056MHz
7.29.1.5. PWRM Register
Prior to WC revision, this register reset by POR/DAFG/ULR. WC revision, reset by POR only. Writing
to NID22h verb 77F will cause reset on all silicon revisions
Register Address
verb F79/779
Bit
Label
7
RSVD
6
RSVD
5
RSVD
4
HPPWD
3
SPKRON
2
DMICPWD
1
MCLKOut
0
RSVD
Type Default
Description
RO 0
Reserved
RO 0
Reserved
RO 0
Reserved
RW 0
Headphone ports are forced off in Aux Audio Mode (including
charge pump)
RW 0
BTL (port D) is forced on in Aux Audio Mode
RW 0
DMIC powered down in Aux Audio Mode (including DAC)
RW 1
MCLK Output Enabler
0 = MCLK Output is disabled in master mode
1 = MCLK is an output in master mode (input in slave mode))
RW 0
Reserved
IDT CONFIDENTIAL
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92HD93