8V97051_16 Datasheet, PDF (28/56 Pages) Integrated Device Technology – Low Power Wideband Fractional RF Synthesizer / PLL

8V97051 Datasheet
Table 11B. Register 6: 1-Bit Digital Lock Detect. Function Description
Name
Description
Function
DigLock
DIGITAL LOCK
0 = PLL Not Locked
1 = PLL Locked (according LDF and LDP in Register 2)
Table 11C. Register 6: 1-Bit Band Select Status (Read Only). Function Description
Name
Description
Function
Band_select_done
BAND_SELECT_DONE
0 = Band Selection Not Complete
1 = Band Selection Complete
Table 11D. Register 6: 2-Bit Extra Lock Detect Precision. Function Description¹
Function
Name
Description
Factory Default
Extra Bit LDP Bits in Register 2
Value
0
00
1
10ns
6ns
LDP_Ext[2:1]
LDP_EXT
00
Extra Lock Detect Precision
0
01
1
0
10
1
3ns
3ns
4ns
4.5ns
0
11
1
1.5ns
1.5ns
NOTE 1. LDP_Ext[2:1] are Extra Lock Detect Precision bits. When these bits are set to 00, then the precision of the Lock Detect precision
only relies on the LDP bit in Register 2, so that the lock detect window is 10ns or 6ns, depending on the LDP bit in Register 2. For
high PFD frequencies, the 6ns window may be larger than the entire ref/FB period. The LDP_ext bits reduce the size of the lock
detect window to the value described in Table 11B, Page 28, allowing an accurate lock detection with higher PFD frequencies.
©2016 Integrated Device Technology, Inc.
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Revision 4, September 22, 2016