ZSSC3224 Datasheet, PDF (27/51 Pages) Integrated Device Technology – High End 24-Bit Sensor Signal Conditioner IC

ZSSC3224 Datasheet
 Power indication (bit 6): 1 if the device is powered (V_DDB on); 0 if not powered. This is needed for the SPI Mode
where the master reads all zeroes if the device is not powered or in power-on reset (POR).
 Busy indication (bit 5): 1 if the device is busy, which indicates that the data for the last command is not available
yet. No new commands are processed if the device is busy.
Note: The device is always busy if the cyclic measurement operation has been set up and started.
 Currently active ZSSC3224 mode (bits [4:3]): 00 = Normal Mode; 01 = Command Mode; 1X = IDT reserved.
 Memory integrity/error flag (bit 2): 0 if integrity test passed; 1 if test failed. This bit indicates whether the checksum-
based integrity check passed or failed. The memory error status bit is calculated only during the power-up
sequence, so a newly written CRC will only be used for memory verification and status update after a subsequent
ZSSC3224 power-on reset (POR) or reset via the RES pin.
 Config Setup (bit 1): This bit indicates which SM_config register is being used for the active configuration:
SM_config1 (12_HEX) or SM_config2 (16_HEX). The two alternate configuration setups allow for two different
configurations of the external sensor channel in order to support up to two application scenarios with the use of only
one sensor-ZSSC3224 pair. This bit is 0 if SM_config1 was selected (default). This bit is 1 if SM_config2 was
selected.
 ALU saturation (bit 0): If the last command was a measurement request, this bit is 0 if any intermediate value and
the final SSC result are in a valid range and no SSC-calculation internal saturation occurred in the arithmetic logic
unit (ALU). If the last command was a measurement request, this bit is 1 if an SSC-calculation internal saturation
occurred. This bit is also 0 for any non-measurement command.
Table 3.3 General Status Byte
Bit
7
6
Meaning
0
Powered?
5
Busy?
43
Mode
2
Memory error?
1
Config Setup
0
ALU Saturation?
Table 3.4 Mode Status
Status[4:3]
00
01
10
11
Mode
Normal Mode (sleep and cyclic operations)
Command Mode
IDT reserved
IDT reserved
Further status information can be provided by the EOC pin. The EOC pin is set high when a measurement and calculation
have been completed (if no interrupt threshold is used, i.e. INT_setup==00_BIN; see section 3.3).
3.5.2. SPI
The SPI Mode is available if the first interface activity after the ZSSC3224 power-up is an active signal at the SS pin. The
polarity and phase of the SPI clock are programmable via the CKP_CKE setting in bits [11:10] in address 02_HEX as
described in Table 3.5. CKP_CKE is two bits: CPHA (bit 10), which selects which edge of SCLK latches data, and CPOL
(bit 11), which indicates whether SCLK is high or low when it is idle. The polarity of the SS signal and pin are
programmable via the SS_polarity setting (bit 9). The different combinations of polarity and phase are illustrated in the
figures below.
© 2016 Integrated Device Technology, Inc
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October 24, 2016