IDT77V1253 Datasheet, PDF (27/44 Pages) Integrated Device Technology – TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
CONTROL AND STATUS INTERFACE
UTILITY BUS
The Utility Bus is a byte-wide interface that provides access to the registers
within the IDT77V1253. These registers are used to select desired operating
characteristics and functions, and to communicate status to external systems.
The Utility Bus is implemented using a multiplexed address and data bus
(AD[7:0]) where the register address is latched via the Address Latch Enable
(ALE) signal.
The Utility Bus interface is comprised of the following pins:
AD[7:0], ALE, CS, RD, WR
Read Operation
Refer to the Utility Bus timing waveforms in Figures 42 - 43. A register read
is performed as follows:
1. Initial condition:
- RD, WR, CS not asserted (logic 1)
- ALE not asserted (logic 0)
2. Set up register address:
- place desired register address on AD[7:0]
- set ALE to logic 1;
- latch this address by setting ALE to logic 0.
3. Read register data:
- Remove register address data from AD[7:0]
- assert CS by setting to logic 0;
- assert RD by setting to logic 0
- wait minimum pulse width time (see AC speci-
fications)
Write Operation
A register write is performed as described below:
1. Initial condition:
- RD, WR, CS not asserted (logic 1)
- ALE not asserted (logic 0)
2. Set up register address:
- place desired register address on AD[7:0]
- set ALE to logic 1;
- latch this address by setting ALE to logic 0.
3. Write data:
- place data on AD[7:0]
- assert CS by setting to logic 0;
- assert WR (logic 0) for minimum time
(according to timing specification); reset WR
complete register write cycle.
to logic 1 to
INTERRUPT OPERATIONS
The IDT77V1253 provides a variety of selectable interrupt and signalling
conditions which are useful both during ‘normal’ operation, and as diagnostic
aids. Refer to the Status and Control Register List section.
Overall interrupt control is provided via bit 0 of the Master Control Registers.
When this bit is cleared (set to 0), interrupt signalling is prevented on the
respective port. The Interrupt Mask Registers allow individual masking of
IDT77V1253
different interrupt sources. Additional interrupt signal control is provided by bit
5 of the Master Control Registers. When this bit is set (=1), receive cell errors
will be flagged via interrupt signalling and all other interrupt conditions are
masked. These errors include:
- Bad receive HEC
- Short (fewer than 53 bytes) cells
- Received cell symbol error
Normal interrupt operations are performed by setting bit 0 and clearing bit
5 in the Master Control Registers. INT (pin 85) will go to a low state when an
interrupt condition is detected. The external system should then interrogate the
77V1253 to determine which one (or more) conditions caused this flag, and reset
the interrupt for further occurrences. This is accomplished by reading the
Interrupt Status Registers. Decoding the bits in these bytes will tell which error
condition caused the interrupt. Reading these registers also:
- clears the (sticky) interrupt status bits in the registers that are read
- resets INT
This leaves the interrupt system ready to signal an alarm for further problems.
LED CONTROL AND SIGNALLING
The LED outputs provide bi-directional LED drive capability of 8 mA. As an
example, the RxLED outputs are described in the truth table:
STATE
PIN VOLTAGE
Cells being received
Low
Cells not being received
High
4781 tbl 10
As illustrated in the following drawing (Figure 31), this could be connected
to provide for a two-LED condition indicator. These could also be different colors
to provide simple status indication at a glance. (The minimum value for R should
be 330Ω, but a value closer to 1 kΩ is recommended).
TxLED Truth Table
STATE
Cells being transmitted
Cells not being transmitted
PIN VOLTAGE
Low
High
4781 tbl 11
RxLED(2:0)
TxLED(2:0)
3.3V
R
(Indicates: Cells
being received
or transmitted)
(Indicates: Cells are
not being received or
R
transmitted)
4781 drw 32
Figure 31.
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