IDT77V1253 Datasheet, PDF (1/44 Pages) Integrated Device Technology – TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS

TRIPLE PORT PHY (PHYSICAL LAYER)
FOR 25.6 AND 51.2 MBPS ATM NETWORKS
IDT77V1253
FEATURES:
• Performs the PHY-Transmission Convergence (TC) and Physical
Media Dependent (PMD) Sublayer functions for three 25.6 Mbps
ATM channels
• Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
• Also operates at 51.2Mbps
• UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface
• 3-Cell Transmit & Receive FIFOs
• LED Interface for status signalling
• Supports UTP Category 3 physical media
• Interfaces to standard magnetics
• Low-Power CMOS
• 3.3V supply with 5V tolerant inputs
• 144-pin PQFP Package (28 x 28 mm)
DESCRIPTION:
The IDT77V1253 is a member of IDT's family of products supporting
Asynchronous Transfer Mode (ATM) data communications and networking.
The IDT77V1253 implements the physical layer for 25.6 Mbps ATM, connect-
ing three serial copper links (UTP Category 3) to one ATM layer device such
as a SAR or a switch ASIC. The IDT77V1253 also operates at 51.2 Mbps, and
is well suited to backplane driving applications.
The 77V1253-to-ATM layer interface is selectable as one of three options:
16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or triple 4-bit DPI
(Data Path Interface).
The IDT77V1253 is fabricated using IDT's state-of-the-art CMOS technol-
ogy, providing the highest levels of integration, performance and reliability, with
the low-power consumption characteristics of CMOS.
FUNCTIONAL BLOCK DIAGRAM - UTOPIA LEVEL 2 MODE
TxCLK
TxDATA[15:0]
TxPARITY
TxSOC
TxEN
TxCLAV
TxADDR[4:0]
MODE[1:0]
RxADDR[4:0]
RxCLK
RxDATA[15:0]
RxPARITY
RxSOC
RxEN
RxCLAV
INT
RST
RD
WR
CS
AD[7:0]
ALE
OSC
TxREF
PHY-ATM
Interface
(UTOPIA or DPI)
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Driver
Clock/Data
Recovery
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Driver
Clock/Data
Recovery
Microprocessor
(Utility Bus)
Interface
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Driver
Clock/Data
Recovery
RxREF
3
3
RxLED[2:0] TxLED[2:0]
+
-
Tx
0
+
-
Rx
0
+
-
Tx
1
+
-
Rx
1
+
- ^{Tx 2}
+
- ^{Rx 2}
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IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
 2004 Integrated Device Technology, Inc. All rights reserved. Product specification subject to change without notice.
DECEMBER 2004
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