IDT72V3640 Datasheet, PDF (27/36 Pages) Integrated Device Technology – 3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II^TM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
tENS
REN
Q0 - Qn
Wx
tENH
tRTS
tA
WCLK
WEN
RT
EF
PAE
HF
tRTS
tENS
1
Wx+1
tSKEW2
1
2
2
tENS
tA
W1 ⁽³⁾
tENH
tA
W2 ⁽³⁾
tENH
tREF
tHF
tREF
tPAES
PAF
tPAFS
4667 drw 16
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100
and 131,072 for the IDT72V36110.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 11. Retransmit Timing (IDT Standard Mode)
27