IDT72V3640 Datasheet, PDF (1/36 Pages) Integrated Device Technology – 3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO
1,024 x 36, 2,048 x 36
IDT72V3640, IDT72V3650
4,096 x 36, 8,192 x 36
IDT72V3660, IDT72V3670
16,384 x 36, 32,768 x 36
IDT72V3680, IDT72V3690
65,536 x36, 131,072 x 36
IDT72V36100, IDT72V36110
FEATURES:
• Choose among the following memory organizations:Commercial
IDT72V3640  1,024 x 36
IDT72V3650  2,048 x 36
IDT72V3660  4,096 x 36
IDT72V3670  8,192 x 36
IDT72V3680  16,384 x 36
IDT72V3690  32,768 x 36
IDT72V36100  65,536 x 36
IDT72V36110  131,072 x 36
• 133 MHz operation (7.5 ns read/write cycle time)
• User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Available in the 128-pin Thin Quad Flat Pack (TQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
WEN _WCLK
D0 -Dn (x36, x18 or x9)
LD SEN
WRITE CONTROL
LOGIC
BE
IP
BM
IW
OW
MRS
PRS
WRITE POINTER
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
INPUT REGISTER
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
OUTPUT REGISTER
READ
RT
CONTROL
LOGIC
RM
RCLK
REN
OE ^{Q0 -Qn (x36, x18 or x9)}
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The SuperSync II FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
© 2001 Integrated Device Technology, Inc.
APRIL 2001
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