ADC1213D Datasheet, PDF (26/40 Pages) NXP Semiconductors – Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps

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Table 17. Register allocation map …continued
Address Register name
(hex)
Access^[1]
Bit 7
0824
Cfg_5_K
R/W*
0
0825
Cfg_6_M
R/W*
0
0826
Cfg_7_CS_N
R/W*
0
0827
Cfg_8_Np
R/W
0
0828
Cfg_9_S
R/W*
0
0829
Cfg_10_HD_CF R/W*
HD
082C
Cfg_01_2_LID
R/W*
0
082D
Cfg_02_2_LID
R/W*
0
084C
Cfg01_13_FCHK R
084D
Cfg02_13_FCHK R
0870
Lane0_0_Ctrl
R/W
0
0871
Lane1_0_Ctrl
R/W
0
0890
ADCA_0_Ctrl
R/W
0
0891
ADCB_0_Ctrl
R/W
0
Bit 6
0
0
CS[0]
0
0
0
0
0
SCR_IN_
MODE
SCR_IN_
MODE
0
0
Bit definition
Bit 5
Bit 4
Bit 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FCHK[7:0]
FCHK[7:0]
LANE_MODE[1:0]
0
LANE_MODE[1:0]
0
ADC_MODE[1:0]
0
ADC_MODE[1:0]
0
[1] an "*" in the Access column means that this register is subject to control access conditions in Write mode.
Bit 2
Bit 1
Bit 0
K[4:0]
0
0
M
N[3:0]
NP[4:0]
0
0
S
0
CF[1:0]
LID[4:0]
LID[4:0]
LANE_
POL
LANE_
POL
0
0
LANE_CLK_
POS_EDGE
LANE_CLK_
POS_EDGE
0
0
LANE_PD
LANE_PD
ADC_PD
ADC_PD
Default
(bin)
0000 1000
0000 0000
0100 0010
0000 1111
0000 0000
0000 0000
0001 1011
0001 1100
0000 0000
0000 0000
0000 0001
0000 0000
0000 0001
0000 0000