82V3001APVG8 Datasheet, PDF (25/28 Pages) Integrated Device Technology – WAN PLL WITH SINGLE REFERENCE INPUT

IDT82V3001A
Table - 18 Input / Output Timing (Continued)
Parameter
Description
t_C2W
t_C4W
t_C8W
t_C16WL
t_C32WH
t_TSPW
t_RSPW
t_F0WL
t_F8WH
t_F16WL
t_0RF
t_S
t_H
t_F16D
t_F32D
t_F32S
t_F32H
t_F32WL
C2o pulse width high or low
C4o pulse width high or low
C8o pulse width high or low
C16o pulse width high or low
C32o pulse width high
TSP pulse width high
RSP pulse width high
F0o pulse width low
F8o pulse width high
F16o pulse width low
Output clock and frame pulse rise or fall time
Input Controls Setup Time
Input Controls Hold Time
F8o to F16o delay
F8o to F32o delay
F32o setup to C32o falling
F32o hold to C32o falling
F32o pulse width low
WAN PLL WITH SINGLE REFERENCE INPUT
Min
Typ
Max
244
122
61
30.5
14.4
486
490
243
123.6
60.9
3
100
100
27.1
30.1
33.1
12
15.8
19
11
11
30.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Fref
8 kHz
Fref
1.544 MHz
Fref
2.048 MHz
t_R8D
t_RW
V_T
t_R15D
t_RW
V_T
t_R2D
t_RW
V_T
F8o
V_T
Figure - 12 Input to Output Timing (Normal Mode)
TIMING CHARACTERISTICS
25
October 15, 2008