82V3001APVG8 Datasheet, PDF (15/28 Pages) Integrated Device Technology – WAN PLL WITH SINGLE REFERENCE INPUT

IDT82V3001A
WAN PLL WITH SINGLE REFERENCE INPUT
3.5.4
FRACTION BLOCK
By applying some algorithms to the incoming E1 signal, the
Fraction_C6 and Fraction_T1 blocks generate C6 and T1 signals
respectively.
3.5.5
DIGITAL CONTROL OSCILLATOR (DCO)
In Normal Mode, the DCO receives three limited and filtered signals
from Loop Filter or Fraction blocks. Based on the received signals, the
DCO generates three digital outputs, 25.248 MHz, 32.768 MHz and
24.704 MHz for C6, E1 and T1 divider respectively.
In Holdover mode, the DCO is running at the same frequency which
is generated by using the storage techniques.
In Freerun mode, the DCO is running at the same frequency as that
of the master clock.
3.5.6
LOCK INDICATOR
In Normal Mode, the LOCK pin will be set to high only when the
following equation is satisfied:
|f_out – f_in| ≤ 0.4 ppm
f_out = the average frequency of the output clock signal from the DPLL
(within 2 seconds)
f_in = the average frequency of the input reference (within 2 seconds)
In other operation modes, the LOCK pin remains low.
3.5.7
OUTPUT INTERFACE
The Output Interface uses three output signals of the DCO to
generate eight types of clock signals and six types of framing signals
totally.
The 32.768 MHz signal is used by the E1_divider to generate five
types of clock signals (C2o, C4o, C8o, C16o and C32o) with nominal
50% duty cycle and six types of framing signals (F0o, F8o, F16o, F32o,
RSP and TSP).
The 24.704 MHz signal is used by the T1_divider to generate two
types of T1 signals (C1.5o and C3o) with nominal 50% duty cycle.
The 25.248 MHz signal is used by the C6_divider to generate a C6o
signal with nominal 50% duty cycle.
All these output signals are synchronous to F8o.
3.6
OSC
The IDT82V3001A can use a clock as the master timing source.
In Freerun Mode, the frequency tolerance at the clock outputs is
identical to that of the source at the OSCi pin. For applications not
requiring an accurate Freerun Mode, the tolerance of the master timing
source may be ±100 ppm. For applications requiring an accurate
Freerun Mode, such as AT&T TR62411, the tolerance of the master
timing source must be no greater than ±32 ppm.
The desired capture range should be taken into consideration when
determining the accuracy of the master timing source. The sum of the
accuracy of the master timing source and the capture range of the
IDT82V3001A will always equal 230 ppm. For example, if the master
timing source is 100 ppm, the capture range will be 130 ppm.
temperature, output rise and fall times, output levels and duty cycle.
For applications requiring ±32 ppm clock accuracy, the following
clock oscillator module may be used.
FOX F7C-2E3-20.0 MHz
Frequency: 20 MHz
Tolerance: 25 ppm 0°C to 70°C
Rise & Fall Time:10 ns (0.33 V 2.97 V 15 pF)
Duty Cycle: 40% to 60%
The output clock should be connected directly (not AC coupled) to
the OSCi input of the IDT82V3001A, and the OSCo output should be left
open as shown in Figure - 9.
IDT82V3001A
OSCi
+3.3 V
OSCo
No Connection
+3.3 V
20MHz OUT
GND
0.1 µF
Figure - 9 Clock Oscillator Circuit
3.7
JTAG
The IDT82V3001A supports IEEE 1149.1 JTAG Scan.
3.8
RESET CIRCUIT
A simple power up reset circuit is shown in Figure - 10. Resistor Rp is
used for protection only and limits current into the RST pin during power
down conditions. The reset low time is not critical but should be greater
than 300 ns. In Figure - 10, the reset low time is about 50 µs.
IDT82V3001A
3.3 V
R
10 kΩ
RST
Rp
C
1 kΩ
1 µF
Figure - 10 Power-Up Reset Circuit
3.6.1
CLOCK OSCILLATOR
When selecting a clock oscillator, numerous parameters must be
considered, including absolute frequency, frequency change over
FUNCTIONAL DESCRIPTION
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October 15, 2008