IDT72805LB Datasheet, PDF (24/26 Pages) Integrated Device Technology – CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18

IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO^TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requiring more than
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
Expansion using one IDT72805LB/72815LB/72825LB/72835LB/72845LBs.
Maximum depth is limited only by signal loading. Follow these steps:
1.The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the
Write Expansion In (WXI) pin of the next device. See Figure 30.
4. The Read Expansion Out (RXO) pin of each device must be tied to the
Read Expansion In (RXI) pin of the next device. See Figure 30.
5. All Load (LD) pins are tied together.
6. The Half-Full flag (HF) is not available in this Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing
together every respective flags for monitoring. The composite PAE and
PAF flags are not precise.
8. In Daisy Chain mode, the flag outputs are single register-buffered and
the partial flags are in asynchronous timing mode.
DATA IN
WRITE CLOCK
WRITE ENABLE
RESET
LOAD
FF/IR
PAF
IDT72845
Vcc
WXOA
WCLKA
WENA
RSA
LDA
RXOA
RCLKA
RENA
OEA
FIFO A
4,096 x 18
DAn
QAn
FLA
FFA/IRA EFA/ORA
PAFA
PAEA
WXIA RXIA
WXOB
WCLKB
WENB
RXOB
RCLKB
RENB
RSB
OEB
DBn
QBn
LDB
FIFO B
4,096 x 18
FFA/IRA EFA/ORA
PAFB
PAEB
WXIB RXIB
FIRST LOAD (FL)
DATA OUT
READ CLOCK
READ ENABLE
OUTPUT ENABLE
EF/OR
PAE
3139 drw 30
Figure 30. Block Diagram of 8,192 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
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