IDT72805LB Datasheet, PDF (20/26 Pages) Integrated Device Technology – CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18

IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFO^TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
WEN
PAE
RCLK
REN
tCLKH
tCLKL
tENS
tENH
n words in FIFO⁽²⁾,
n + 1words in FIFO⁽³⁾
tSKEW2 ⁽⁴⁾
tPAES
n + 1 words in FIFO⁽²⁾,
n + 2 words in FIFO⁽³⁾
tENS
tPAES
tENH
n Words in FIFO⁽²⁾,
n + 1 words in FIFO⁽³⁾
3139 drw 22
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAF
RCLK
REN
tCLKH
tCLKL
tENS
tENH
D-(m+1) Words in FIFO
tPAFS
D - m Words in FIFO
tENS
tSKEW2⁽³⁾
tENH
tPAFS
D -(m+1) Words
in FIFO
3139 drw 23
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72805, 512 for the IDT72815, 1,024 for the IDT72825, 2,048 for the IDT72835 and 4,096 for the IDT72845.
In FWFT Mode: D = 257 for the IDT72805, 513 for the IDT72815, 1,025 for the IDT72825, 2,049 for the IDT72835 and 4,097 for the IDT72845.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
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