IDT72261LA Datasheet, PDF (23/27 Pages) Integrated Device Technology – CMOS SuperSync FIFO

IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9
t CLKH
WCLK
WEN
PAE
RCLK
t CLKL
t ENS
t ENH
n words in FIFO ^(2),
n+1 words in FIFO ⁽³⁾
t SKEW2 ⁽⁴⁾
1
t PAE
2
REN
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
n+1 words in FIFO ^(2),
n+2 words in FIFO ⁽³⁾
t ENS
1
t ENH
t PAE
2
n words in FIFO ^(2),
n+1 words in FIFO ⁽³⁾
4671 drw 20
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
HF
RCLK
REN
tCLKH
tCLKL
tENS
D/2 words in FIFO⁽¹⁾,
[ ] D-1
2
+1
words in FIFO⁽²⁾
tENH
tHF
D/2 + 1 words in FIFO⁽¹⁾,
[ ] D-1
2 ⁺²
words in FIFO⁽²⁾
tHF
tENS
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 16,384 for the IDT72261LA and 32,768 for the IDT72271LA.
2. For FWFT mode: D = maximum FIFO depth. D = 16,385 for the IDT72261LA and 32,769 for the IDT72271LA.
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
23
D/2 words in FIFO⁽¹⁾,
[ ] D-1
2 ⁺¹
words in FIFO⁽²⁾
4671 drw 21