IDT72261LA Datasheet, PDF (1/27 Pages) Integrated Device Technology – CMOS SuperSync FIFO

CMOS SuperSync FIFO^™
16,384 x 9
32,768 x 9
IDT72261LA
IDT72271LA
FEATURES:
• Choose among the following memory organizations:
IDT72261LA 16,384 x 9
IDT72271LA 32,768 x 9
• Pin-compatible with the IDT72281/72291 SuperSync FIFOs
• 10ns read/write cycle time (8ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Retransmit operation with fixed, low first word data latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write clocks (permit reading and writing
simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT72261LA/72271LA are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
• The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written
to an empty FIFO to the time it can be read, is now fixed and short. (The
variable clock cycle counting delay associated with the latency period found
on previous SuperSync devices has been eliminated on this SuperSync
family.)
FUNCTIONAL BLOCK DIAGRAM
WEN _WCLK
D0 -D8
LD SEN
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
16,384 x 9
32,768 x 9
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
MRS
PRS
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
RT
LOGIC
RCLK
REN
Q0 -Q8
OE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
 2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
4671 drw 01
SEPTEMBER 2002
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