IDT8T49N008I Datasheet, PDF (22/38 Pages) Integrated Device Technology – Fourth Generation FemtoClock NG PLL technology

IDT8T49N008I Data Sheet
PROGRAMMABLE FEMTOCLOCK^® NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HCSL and other differential
signals. Both V_SWING and V_OH must meet the V_PP and V_CMR input
requirements. Figures 3A to 3D show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
LVPECL
3.3V
3.3V
CLK
nCLK
Differential
Input
Figure 3A. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
R2
50Ω
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
*R3
*R4
HCSL
3.3V
CLK
nCLK
Differential
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 3C. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014
22
©2014 Integrated Device Technology, Inc.