IDT70T3539M Datasheet, PDF (22/26 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
The IDT70T3539M features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70T3539M can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 72-bits or wider.
A19
IDT70T3539M CE0
IDT70T3539M CE0
CE1 VDD
CE1 VDD
Control Inputs
Control Inputs
IDT70T3539M CE1
CE0
Control Inputs
IDT70T3539M CE1
CE0
Control Inputs
5678 drw 22
Figure 4. Depth and Width Expansion with IDT70T3539M
BE,
R/W,
OE,
CLK,
ADS,
REPEAT,
CNTEN
JTAG Functionality and Configuration
The IDT70T3539M is composed of two independent memory arrays,
and thus cannot be treated as a single JTAG device in the scan chain.
The two arrays (A and B) each have identical characteristics and
commands but must be treated as separate entities in JTAG operations.
.Please ^{refer to Figure 5.}
JTAG signaling must be provided serially to each array and utilize the
information provided in the Identification Register Definitions, Scan
Register Sizes, and System Interface Parameter tables. Specifically,
commands for Array B must precede those for Array A in any JTAG
operations sent to the IDT70T3539M. Please reference Application Note
AN-411, "JTAG Testing of Multichip Modules" for specific instructions on
performing JTAG testing on the IDT70T3539M. AN-411 is available at
www.idt.com.
TDI
TCK
TMS
TRST
Array A
TDOA
IDT70T3539M
TDIB
Array B
TDO
Figure 5. JTAG Configuration for IDT70T3539M
5678drw 23
6.2422