IDT70T3539M Datasheet, PDF (1/26 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 2.5V
512K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
PRELIMINARY
IDT70T3539M
Features:
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed data access}
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
◆ _{Selectable Pipelined or Flow-Through output mode}
◆ _{Counter enable and repeat features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Interrupt and Collision Detection Flags}
◆ _{Full synchronous operation on both ports}
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{Dual Cycle Deselect (DCD) for Pipelined Output Mode}
◆ _{2.5V (±100mV) power supply for core}
◆ _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on
each port
◆ _{Includes JTAG functionality}
◆ _{Industrial temperature range (-40°C to +85°C) is}
available at 133MHz
◆ _{Available in a 256-pin Ball Grid Array (BGA)}
Functional Block Diagram
BE3L
BE3R
BE2L
BE2R
B E1 L
BE1R
BE0L
BE0R
FT/PIP EL
0a 1a
1/0
a
0b 1b 0c 1c
b
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
1/0
a
FT/PIPER
R/WL
R/WR
CE0L
1
CE1L
0
1/0
OEL
BBBBB BBB
WWWWW WWW
01233 210
L L L L R RRR
D ou t0-8_ L
D ou t9-17 _L
D ou t18-2 6_L
D ou t27-3 5_L
D ou t0-8_ R
Do ut9 -17_ R
D out 18- 26 _R
D out 27- 35 _R
CE0R
1
CE1R
0
1/0
OER
FT/PIPEL
1d 0d 1c 0c 1b 0b 1a 0a
0/1
a bc d
512K x 36
MEMORY
ARRAY
0a 1a 0b 1b 0c 1c 0d 1d
0/1
d c ba
,
FT/PIPER
I/O0L - I/O35L
Din_L
Din_R
I/O0R - I/O35R
CLKL
A18L
A0L
RE PEATL
ADSL
CN TENL
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A18R
CLKR
A0R
REPEATR
ADSR
CNTENR
COL L
INTL
CE 0 L
CE1L
R/WL
INTERRUPT
COL LISION
DE TE CTION
LOGIC
CE0 R
CE1 R
R /W R
TDI
TDO
COLR
INTR
Z ZL(1 ⁾
ZZ
CONTROL
LOGIC
ZZR(1)
NOTE:
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and
the sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
©2004 Integrated Device Technology, Inc.
,
TCK
JTAG
TMS
TRST
5678 drw 01
APRIL 2004
DSC 5678/5