RC32434 Datasheet, PDF (21/53 Pages) Integrated Device Technology – IDT TInterprise Integrated Communications Processor

IDT RC32434
DDRCKP
DDRCKN
DDRCSN
DDRADDR[13:0]
DDRCMD¹
DDRCKE
NOP
DDRBA[1:0]
Tdo_7m
Tdo_7m
RowA
Tdo_7m
ACTV
NOP
Col A0 Col A2
WR
WR
NOP
NOP NOP
Tdo_7m
BNKx
BNKx
NOP
NOP
DDRDQSx
DDRDM[1:0]
Tdo_7l
Tdo_7l
FF
DM0 DM1 DM3
FF
DM2
DDRDQSx
DDRDATA[15:0]²
Tdo_7k
Tdo_7k
D0 D1 D2
D3
1 _{DDRCMD contains DDRRASN, DDRCASN and DDRWEN.}
2 _{DDRDATA is either 32-bits or 16-bits wide depending on the DBW control bit in DDRC Register}
(see Chapter 7, DDR Controller, in the RC32434 User Reference Manual).
Figure 7 DDR SDRAM Timing Waveform — Write Access
Signal
Symbol
Reference
Edge
266MHz
Min Max
300MHz
Min Max
350MHz
Min Max
400MHz
Min Max
Unit
Memory and Peripheral Bus¹
MADDR[21:0] Tdo_8a EXTCLK rising 0.4 4.5 0.4 4.5 0.4 4.5 0.4 4.5
ns
Tdz_8a²
—
—
—
—
—
—
—
—
ns
Tzd_8a²
—
—
—
—
—
—
—
—
ns
MADDR[25:22] Tdo_8b EXTCLK rising 0.4 4.5 0.4 4.5 0.4 4.5 0.4 4.5
ns
Tdz_8b²
—
—
—
—
—
—
—
—
ns
Tzd_8b²
—
—
—
—
—
—
—
—
ns
Table 8 Memory and Peripheral Bus AC Timing Characteristics (Part 1 of 2)
Condi-
tions
Timing
Diagram
Reference
See Figures 8
and 9.
21 of 53
January 19, 2006