RC32434 Datasheet, PDF (1/53 Pages) Integrated Device Technology – IDT TInterprise Integrated Communications Processor

IDT^TM Interprise^TM Integrated
Communications Processor
RC32434
Device Overview
The RC32434 is a member of the IDT™ Interprise™ family of PCI
integrated communications processors. It incorporates a high perfor-
mance CPU core and a number of on-chip peripherals. The integrated
processor is designed to transfer information from I/O modules to main
memory with minimal CPU intervention, using a highly sophisticated
direct memory access (DMA) engine. All data transfers through the
RC32434 are achieved by writing data from an on-chip I/O peripheral to
main memory and then out to another I/O module.
Features
x _{32-bit CPU Core}
– MIPS32 instruction set
– Cache Sizes: 8KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
– 16 dual-entry JTLB with variable page sizes
– 3-entry instruction TLB
– 3-entry data TLB
– Max issue rate of one 32x16 multiply per clock
– Max issue rate of one 32x32 multiply every other clock
– CPU control with start, stop, and single stepping
– Software breakpoints support
– Hardware breakpoints on virtual addresses
– ICE Interface that is compatible with v2.5 of the EJTAG Spec-
ification
x _{PCI Interface}
– 32-bit PCI revision 2.2 compliant
– Supports host or satellite operation in both master and target
modes
– Support for synchronous and asynchronous operation
– PCI clock supports frequencies from 16 MHz to 66 MHz
– PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
– I₂O “like” PCI Messaging Unit
x _{Ethernet Interface}
– 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant
– Supports MII or RMII PHY interface
– Supports 64 entry hash table based multicast address filtering
– 512 byte transmit and receive FIFOs
– Supports flow control functions outlined in IEEE Std. 802.3x-
1997
x _{DDR Memory Controller}
– Supports up to 256MB of DDR SDRAM
– 1 chip select supporting 4 internal DDR banks
– Supports a 16-bit wide data port using x8 or x16 bit wide DDR
SDRAM devices
– Supports 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1Gb DDR
SDRAM devices
– Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
– Automatic refresh generation
Block Diagram
ICE
DDR
(16-bit)
MIPS-32
CPU Core
EJTAG
D. Cache
MMU
I. Cache
PMBus
DDR
Controllers
MII/RMII
Interrupt
Controller
:
:
3 Counter
Timers
1 Ethernet
10/100
Interface
IPBus^TM
I²C Bus
I²C
Controller
DMA
Controller
Arbiter
Memory & I/O
Controller
Bus/System
Integrity
Monitor
1 UART
(16550)
GPIO
Interface
SPI
Controller
PCI
Master/Target
Interface
PCI Arbiter
(Host Mode)
Memory &
Peripheral Bus (8-bit)
Serial Channel ^{GPIO Pins SPI Bus}
PCI Bus
 2005 Integrated Device Technology, Inc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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January 19, 2006
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