ICS9LPRS525_11 Datasheet, PDF (21/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
Revision History
Rev. Issue Date Who Description
0.1 7/21/2008 RDW Initial Release
1. Updated pinout to remove Vout reference on pin 40
0.2 08/060/08 RDW 2. Updated VDD_IO pin descriptions to show 1.05V to 3.3V operation
1. Fixed Pagination of Pin Descriptions
2. Changed reference to PCI3 Config Table in Pindes to match table name
0.3 8/8/2008 RDW 3. Added Byte 29 for Slew Rate control
Page #
-
1, 3
2,3,17
1) Byte 11, bit 5 is now reserved.
2) Byte 29, bits 7:6 default to 0.8X slew rate (‘10’)
3) Removed reference to STOP drive mode in Power management table.
4) Corrected REF slew rate control from Byte 29b3 to Byte 29b2.
5) Clarified description of Byte 11, bits 2 and 3 to reflect CK505 ME clock selection table.
0.4 10/10/2008 RDW 6) Marked as Reserved all bits that are not in the 56-pin version of the device
Various
1) updated tables 2, 6 and 7 to clarify interaction of Config Modes with SRC1
10, 11, 19,
0.5 4/28/2009 RDW 2) Updated ordering revision to A
20
A 4/28/2009 RDW Released to final
B 1/21/2010 RDW Updated Power Groups table
4
C 4/20/2010 RDW Updated Abs Max table with Case Temp. parameter
5
D 1/31/2011 RDW Updated cycle to cycle jitter for SRC outputs to 85ps from 125ps.
6
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