ICS9LPRS365BGLFT Datasheet, PDF (21/28 Pages) Integrated Device Technology – 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit Pin
Name
Description
7
SRC3_OE
Output enable for SRC3
6
SATA/SRC2_OE
Output enable for SATA/SRC2
5
SRC1_OE
Output enable for SRC1
4
SRC0/DOT96_OE
Output enable for SRC0/DOT96
3
CPU1_OE
Output enable for CPU1
2
CPU0_OE
Output enable for CPU0
1
PLL1_SSC_ON
Enable PLL1's spread modulation
0
PLL3_SSC_ON
Enable PLL3's spread modulation
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Spread Disabled
Spread Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Spread Enabled
Spread Enabled
Default
1
1
1
1
1
1
1
1
Byte 5 Clock Request Enable/Configuration Register
Bit Pin
Name
Description
7
CR#_A_EN
Enable CR#_A (clk req),
PCI0_OE must be = 0 for this bit to take effect
6
CR#_A_SEL
Sets CR#_A to control either SRC0 or SRC2
5
CR#_B_EN
Enable CR#_B (clk req)
4
CR#_B_SEL
Sets CR#_B -> SRC1 or SRC4
3
CR#_C_EN
Enable CR#_C (clk req)
2
CR#_C_SEL
Sets CR#_C -> SRC0 or SRC2
1
CR#_D_EN
Enable CR#_D (clk req)
0
CR#_D_SEL
Sets CR#_D -> SRC1 or SRC4
Type
0
1
RW Disable CR#_A Enable CR#_A
RW CR#_A -> SRC0 CR#_A -> SRC2
RW Disable CR#_B Enable CR#_B
RW CR#_B -> SRC1 CR#_B -> SRC4
RW Disable CR#_C Enable CR#_C
RW CR#_C -> SRC0 CR#_C -> SRC2
RW Disable CR#_D Enable CR#_D
RW CR#_D -> SRC1 CR#_D -> SRC4
Default
0
0
0
0
0
0
0
0
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Bit Pin
Name
Description
Type
7
CR#_E_EN
Enable CR#_E (clk req) -> SRC6
RW
6
CR#_F_EN
Enable CR#_F (clk req) -> SRC8
RW
5
CR#_G_EN
Enable CR#_G (clk req) -> SRC9
RW
4
CR#_H_EN
Enable CR#_H (clk req) -> SRC10
RW
3
Reserved
Reserved
RW
2
Reserved
Reserved
RW
0
Disable CR#_E
Disable CR#_F
Disable CR#_G
Disable CR#_H
SSCD_STP_CRTL
1
If set, LCD_SS stops with PCI_STOP#
RW Free Running
0
SRC_STP_CRTL
If set, SRCs stop with PCI_STOP#
RW Free Running
1
Enable CR#_E
Enable CR#_F
Enable CR#_G
Enable CR#_H
Stops with
PCI_STOP#
assertion
Stops with
PCI_STOP#
assertion
Default
0
0
0
0
0
0
0
0
Byte 7 Vendor ID/ Revision ID
Bit Pin
Name
7
Rev Code Bit 3
6
Rev Code Bit 2
5
Rev Code Bit 1
4
Rev Code Bit 0
3
Vendor ID bit 3
2
Vendor ID bit 2
1
Vendor ID bit 1
0
Vendor ID bit 0
Description
Revision ID
Vendor ID
ICS is 0001, binary
Type
R
R
R
R
R
R
R
R
0
1
Vendor specific
Default
0
0
1
0
0
0
0
1
1218—09/09/09
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