IDT70P258 Datasheet, PDF (20/23 Pages) Integrated Device Technology – VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM

IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
MASTER
Dual Port
SRAM
BUSYL
CE
BUSYR
SLAVE
Dual Port
SRAM
BUSYL
CE
BUSYR
BUSYL
MASTER
Dual Port
SRAM
BUSYL
CE
BUSYR
SLAVE
Dual Port
SRAM
BUSYL
CE
BUSYR
BUSYR
,
5675 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70P258/248 SRAMs.
Functional Description
The IDT70P258/248 provides two ports with separate control, ad-
dress and I/O pins that permit independent access to any location in
memory. The IDT70P258/248 has an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location 1FFE
(HEX) (FFE for IDT70P248), where a write is defined as the CE=R/W=VIL
per Truth Table III. The left port clears the interrupt by accessing address
location 1FFE when CER = OER = VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port writes
to memory location 1FFF (HEX) (FFF for IDT70P248) and to clear the
interrupt flag (INTR), the right port must read the memory location 1FFF.
The message (16 bits) at 1FFE or 1FFF is user-defined, since it is an
addressable SRAM location. If the interrupt function is not used, address
locations 1FFE and 1FFF are not used as mail boxes, but as part of the
random access memory. Refer to Truth Table IIII for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The BUSY pin can then be used to stall the access
until the operation on the other side is completed. If a write operation has
been attemp-ted from the side that receives a BUSY indication, the write
signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The busy outputs on the IDT 70P258/248 SRAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate. If
these SRAMs are being expanded in depth, then the BUSY indication for
the resulting array requires the use of an external AND gate.
Width Expansion with BUSY Logic
Master/Slave Arrays
When expanding an IDT70P258/248 SRAM array in width while
using busy logic, one master part is used to decide which side of the SRAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70P258/248 SRAM the BUSY pin is an output if the part is used as a
master (M/S pin = VDD), and the BUSY pin is an input if the part used as
a slave (M/S pin = VSS) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
Input Read Register
The Input Read Register (IRR) of the IDT70P258/248 captures the
status of two external binary input devices connected to the Input Read pins
(e.g. DIP switches). The contents of the IRR are read as a standard
memory access to address x0000 from either port and the data is output
via the standard I/Os (Truth Table VI). During Input Register reads I/O0
- I/O1 are valid bits and I/O2 - I/O15 are "Dont' Care". Writes to address
x0000 are not allowed from either port. When SFEN = VIL, the IRR is active
and address x0000 is not available for standard memory operations.
When SFEN = VIH, the IRR is inactive and address x0000 can be used
as part of the main memory. The IRR supports inputs up to 3.5V (VIL < 0.4V,
VIH > 1.4V). Refer to Figure 3 and Truth Table VI for Input Read Register
operation.
62.402