IDT70P258 Datasheet, PDF (1/23 Pages) Integrated Device Technology – VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM

VERY LOW POWER 1.8V
8K/4K x 16 DUAL-PORT
STATIC RAM
IDT70P258/248L
Features
◆ _{True Dual-Ported memory cells which allow simultaneous}
reads of the same memory location
◆ _{High-speed access}
– Industrial: 55ns (max.)
◆ _{Low-power operation}
IDT70P258/248L
Active: 27mW (typ.)
Standby: 3.6µW (typ.)
◆ _{Separate upper-byte and lower-byte control for multiplexed}
bus compatibility
◆ _{IDT70P258/248 easily expands data bus width to 32 bits or}
more using the Master/Slave select when cascading more
than one device
◆ _{Supports 3.0V, 2.5V and 1.8V I/O's}
◆ _{M/S = VDD for BUSY output flag on Master}
M/S = VSS for BUSY input on Slave
◆ _{Input Read Register}
◆ _{Output Drive Register}
◆ _{BUSY and Interrupt Flag}
◆ _{On-chip port arbitration logic}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{LVTTL-compatible, single 1.8V (±100mV) power supply}
◆ _{Available in 100 Ball 0.5mm-pitch BGA}
◆ _{Industrial temperature range (-40°C to +85°C)}
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
I/O8L-I/O15L
I/O0L-I/O7L
BUSYL^(2,3)
A12L⁽¹⁾
A0L
I/O
Control
I/O
Control
Address
Decoder
MEMORY
ARRAY
Address
Decoder
CEL
OEL
R/WL
IRR0,IRR1
13
CEL
OEL
R/WL
SEML
INTL⁽³⁾
NOTES:
1. A12X is a NC for IDT70P248.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
©2004 Integrated Device Technology, Inc.
INPUT
READ REGISTER
AND
OUTPUT
DRIVE REGISTER
SFEN
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
1
CER
OER
R/WR
OD R0 - ODR4
13
CER
OER
R/WR
,
I/O8R-I/O15R
I/O0R-I/O7R
BUSYR^(2,3)
A12R⁽¹⁾
A0R
SEMR
INTR⁽³⁾
5675 drw 01
APRIL 2004
DSC-5675/4