ICS9ZX21901CKLFT Datasheet, PDF (2/16 Pages) Integrated Device Technology – 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI

9ZX21901C
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Pin Configuration
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDDA 1
54 ^OE11#
GNDA 2
53 ^DIF_11#
IREF 3
52 ^DIF_11
100M_133M# 4
51 ^OE10#
HIBW_BYPM_LOBW# 5
50 ^DIF_10#
CKPWRGD_PD# 6
49 ^DIF_10
GND 7
48 ^OE9#
VDDR 8
9ZX21901C
47 ^DIF_9#
DIF_IN 9
DIF_IN# 10
SMB_A0_tri 11
NOTE: DFB_OUT pins must be terminated identically
to the regular DIF outputs
46 ^DIF_9
45 ^VDD
44 ^GND
SMBDAT 12
43 ^OE8#
SMBCLK 13
42 ^DIF_8#
SMB_A1_tri 14
41 ^DIF_8
NC 15
40 ^OE7#
NC 16
39 ^DIF_7#
DFB_OUT# 17
38 ^DIF_7
DFB_OUT 18
37 ^OE6#
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
72-pin MLF
Functionality at Power Up (PLL Mode)
100M_133M#
DIF_IN
(MHz)
1
100.00
0
133.33
DIF
(MHz)
DIF_IN
DIF_IN
PLL Operating Mode Readback Table
HiBW_BypM_LoBW# Byte0, bit 7
Low (Low BW)
0
Mid (Bypass)
0
High (High BW)
1
Byte 0, bit 6
0
1
1
PLL Operating Mode
HiBW_BypM_LoBW#
MODE
Low
PLL Lo BW
Mid
High
Bypass
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
Tri-level Input Thresholds
Level
Voltage
Low
<0.8V
Mid
1.2<Vin<1.8V
High
Vin > 2.2V
IDT^® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Power Connections
Pin Number
VDD
1
8
21, 31, 45,
58, 68
GND
2
7
26, 44, 63
Description
Analog PLL
Analog Input
DIF clocks
9ZX21901 SMBus Addressing
Pin
SMBus Address
SMB_A1_tri SMB_A0_tri (Rd/Wrt bit = 0)
0
0
D8
0
M
DA
0
1
DE
M
0
C2
M
M
C4
M
1
C6
1
0
CA
1
M
CC
1
1
CE
1648H- 12/08/11
2