ICS9ZX21901CKLFT Datasheet, PDF (10/16 Pages) Integrated Device Technology – 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI

9ZX21901C
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
General SMBus serial interface information for the 9ZX21901C
(See also 9ZX21901 SMBus Addressing on page 2)
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address XX _(H)
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the data byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address XX
(H)
• IDT clock will acknowledge
• Controller (host) sends the begining byte
location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read addressYY _(H)
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N + X -1
• IDT clock sends Byte 0 through byte X (if X_(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T
starT bit
IDT (Slave/Receiver)
Slave Address XX_(H)
WR
WRite
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
ACK
ACK
ACK
Byte N + X - 1
P
stoP bit
ACK
Note: XX_(H) is defined by SMBus address select pins.
IDT^® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Index Block Read Operation
Controller (Host)
T
starT bit
IDT (Slave/Receiver)
Slave Address XX_(H)
WR
WRite
Beginning Byte = N
RT
Repeat starT
ACK
ACK
Slave Address YY_(H)
RD
ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P
stoP bit
10
Byte N + X - 1
1648H- 12/08/11