ICS97U870 Datasheet, PDF (2/13 Pages) Integrated Device Technology – Feedback pins for input to output synchronization

ICS97U8 7 0
Advance Information
Pin Descriptions
Terminal
Name
AGND
AV
DD
CLK_INT
CLK_INC
FB_INT
FB_INC
FB_OUTT
FB_OUTC
OE
OS
GND
V_DDQ
CLKT[0:9]
CLKC[0:9]
NB
Description
Analog Ground
Analog power
Clock input with a (10K-100K Ohm) pulldown resistor
Complentary clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Complementary feedback clock input
Feedback clock output
Complementary feedback clock output
Output Enable (Asynchronous)
Output Select (tied to GND or V_DDQ)
Ground
Logic and output power
Clock outputs
Complementary clock outputs
No ball
Electrical
Characteristics
Ground
1.8 V nominal
Differential input
Differential input
Differential input
Differential input
Differential output
Differential output
LVCMOS input
LVCMOS input
Ground
1.8V nominal
Differential outputs
Differential outputs
The PLL clock buffer, ICS97U870, is designed for a V_DDQ of 1.8 V, a AV_DD of 1.8 V and differential data input and output
levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97U870 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential
pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC).
The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the
LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/
FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a
program pin that must be tied to GND or V_DDQ.When OS is high, OE will function as described above.When OS is low,
OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC).When AV_DD is grounded,
the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time t_STAB.
The PLL in ICS97U870 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).ICS97U870
is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97U870 is characterized for operation from 0°C to 70°C.
0817—07/07/03
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