ICS9220 Datasheet, PDF (2/17 Pages) Integrated Device Technology – Programmable RambusTM XDRTM Clock Generator

ICS9220
Pin Descriptions
PIN #
1
2
PIN NAME
AVDD2.5
AGND
3
IREFY
4
AGND
5
CLK_INT
6
CLK_INC
7
VDD2.5
8
GND
9
SMBCLK
10
SMBDAT
11
OE
12
AS1
13
AS2
14
BYPASS#/PLL
15
VDD2.5
16
GND
17
GND
18
ODCLK_C1
19
ODCLK_T1
20
GND
21
VDD2.5
22
VDD2.5
23
GND
24
ODCLK_C0
25
ODCLK_T0
26
GND
27
GND
28
VDD2.5
PIN TYPE
PWR
PWR
OUT
PWR
IN
IN
PWR
PWR
IN
I/O
IN
IN
IN
IN
PWR
PWR
PWR
OUT
OUT
PWR
PWR
PWR
PWR
OUT
OUT
PWR
PWR
PWR
DESCRIPTION
2.5V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
This pin establishes the reference current for the differential clock
pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current.
Analog Ground pin for Core PLL
"True" reference clock input.
"Complementary" reference clock input.
Power supply, nominal 2.5V
Ground pin.
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Default SMBus Address Select.
Default SMBus Address Select.
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Power supply, nominal 2.5V
Ground pin.
Ground pin.
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
Ground pin.
Power supply, nominal 2.5V
Power supply, nominal 2.5V
Ground pin.
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
Ground pin.
Ground pin.
Power supply, nominal 2.5V
1227G—11/05/07
2