ICS9220 Datasheet, PDF (1/17 Pages) Integrated Device Technology – Programmable RambusTM XDRTM Clock Generator

Integrated
Circuit
Systems, Inc.
ICS9220
Programmable Rambus^TM XDR^TM Clock Generator
General Description
Features
The ICS9220 clock generator provides Programmable ^{• 300 - 700 MHz clock source}
clock signals to support the Rambus XDR^TM memory _{• 2 open-drain differential output drives with short}
subsystem and Redwood logic interface. The ICS9220
term jitter < 40ps
has been optimized for 100MHz reference input that may
or may not be modulated for spread spectrum. The
•
Spread spectrum compatible
ICS9220 provides 2 differential clock pairs in a space • Reference clock is differential or single-ended
saving 28-pin TSSOP package and provides an off-the-
100MHz
shelf high-performance interface solution.
• SMBus programmability for:
Figure 1 shows the major components of the ICS9220
- frequency multiplier
XDR Clock Generator. These include the a PLL, a Bypass
- output enable
Multiplexer and two differential output buffers. The outputs
can be disabled by a logic low on the OE pin. An output
- operating mode
is enabled by the combination of the OE pin being high, • Support systems where XDR subsystem is
and 1 in its SMBus Output control register bit.
asynchronous to other system clocks
• 2.5V power supply
The PLL receives a reference clock, CLK_INT/C and
outputs a clock signal at a frequency equal to the input
frequency times a multiplier. Table 2 shows the multipliers
selectable via the SMBus interface. This clock signal is
then fed to the differential output buffers to drive the
enabled clocks. Disabled outputs are set to Hi-Z. The
Bypass mode routes the input clock, CLK_INT/C, directly
to the differential output buffers, bypassing the PLL.
Up to four ICS9220 devices can be cascaded on the same
SMBus. Table 3 shows the SMBus addressing and control
for the four devices.
Block Diagram
OE
BYPASS#/PLL
CLK_INT
CLK_INC
SMBCLK
OE
RegA
Bypass
MUX
OE
RegB
PLL
SMBDAT AS1
AS2
1227G—11/05/07
Pin Configuration
ODCLK_T0
ODCLK_C0
ODCLK_T1
ODCLK_C1
AVDD2.5 1
AGND 2
IREFY 3
AGND 4
CLK_INT 5
CLK_INC 6
VDD2.5 7
GND 8
SMBCLK 9
SMBDAT 10
OE 11
AS1 12
AS2 13
BYPASS#/PLL 14
28 VDD2.5
27 GND
26 GND
25 ODCLK_T0
24 ODCLK_C0
23 GND
22 VDD2.5
21 VDD2.5
20 GND
19 ODCLK_T1
18 ODCLK_C1
17 GND
16 GND
15 VDD2.5
28-Pin 4.4mm TSSOP
XDR is a trademark of Rambus