ICS8732-01 Datasheet, PDF (2/17 Pages) Integrated Device Technology – Maximum output frequency

ICS8732-01
LOW VOLTAGE, LOW SKEW
3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 8, 32,
39, 40
2, 3,
4, 5
6,
13, 17,
27, 34,
45, 52
V_CCO
QA0, nQA0,
QA1, nQA1
V_EE
7
PLL_SEL
9, 10,
11, 12
14
QA2, nQA2,
QA3, nQA3
DIV_SELA1
15
16, 26,
46
DIV_SELA0
V_CC
Power
Output
Output supply pins.
Differential output pair. LVPECL interface levels.
Power
Negative supply pins.
Input
Pullup
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
Output
Differential output pairs. LVPECL interface levels.
Input
Input
Pulldown
Pulldown
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
Power
Core supply pins.
18
CLK1
Input Pulldown LVCMOS / LVTTL reference clock input.
19
nCLK0
Input Pullup Inverting differential clock input.
20
CLK0
Input Pulldown Non-inverting differential clock input.
21
CLK_SEL
Input
Pulldown
Clock select input. When LOW, selects CLK0, nCLK0.
When HIGH, selects CLK1. LVCMOS / LVTTL interface levels.
22
V_CCA
Power
23
nc
Unused
Analog supply pin.
No connect.
24
25
28, 29,
30, 31
33
35, 36,
37, 38
41, 42,
43, 44
47
48
49
50
51
DIV_SELB1
DIV_SELB0
QB0, nQB0,
QB1, nQB1
MR
QB2, nQB2,
QB3, nQB3
QFB1, nQFB1,
QFB0, nQFB0
FB_IN
nFB_IN
FBDIV_SEL0
FBDIV_SEL1
FBDIV_SEL2
Input
Input
Output
Input
Output
Output
Input
Input
Input
Input
Input
Pulldown
Pulldown
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
Differential output pairs. LVPECL interface levels.
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Differential output pairs. LVPECL interface levels.
Differential feedback output pairs. LVPECL interface levels.
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Feedback input to phase detector for regenerating clocks
with "zero delay".
Feedback input to phase detector for regenerating clocks
with "zero delay".
Selects divide value for differential feedback output pairs.
LVCMOS / LVTTL interface levels.
Selects divide value for differential feedback output pairs.
LVCMOS / LVTTL interface levels.
Selects divide value for differential feedback output pairs.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8732AY-01
www.idt.com
REV. E MAY 2, 2013
2